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Re: [Phys-l] RC Disharge Analysis



Well John, the reason I didn't draw any diagrams is because your ASCII drawings always come across virtually worthless on my screen, so I figure it isn't worth the effort to try to draw a diagram for sending through PHYS-L. I can't make out anything from the "diagrams" in your posts.

The circuit is in virutally every calculus-based physics book. I gave page references to one of the books and could give others. But it would seem you could draw a circuit from my description.

Draw a rectangle, consider the rectangle a loop of wire. Cut the left wire and put a capacitor in it. Cut the right wire and put a resistor in it. Cut the bottom wire and put a switch in it. Leave the top wire as a wire.

Start with the switch open and the capacitor charged. Let's say the bottom plate is the positive plate of the capacitor.

This is the diagram on page 876 of Serway (figure 28.21). It is also Figure 26-37 in Tipler, except the Tipler figure has the top plate of the capacitor as positive.

Let's go with the Serway figure (bottom plate positive).

Close the switch and the current flows counterclockwise around the loop. That means the current is flowing upward through the resistor making its bottom end positive. If we apply the loop theorem around the loop in the current-flow direction (CCW) the resistor is a drop in voltage and the capacitor is an increase in voltage. The loop theorem yields... +q/C - IR = 0.

But Serway says -q/C - IR = 0, which makes no sense, and then goes on to say I = dq/dt which is the standard definition of current.

Tipler says q/C -IR = 0, which makes sense, but then goes on to say I = -dq/dt because I is the rate of decrease of charge on the capacitor. That also makes sense, but it is not the definition of current, and students wonder why it is sometimes okay to write I = dq/dt while other times we have to write I = -dq/dt.

I prefer the Tipler method because Serway clearly has an error in the application of the loop theorem. But how do you answer the students as they question why current isn't always dq/dt (which is what Serway says)?

On John's method three, the figure is garbled on my screen, but it looks like one of the signs of V = Q/C or V=IR must be wrong because the capacitor plate connected to the resistor would be the higher potential of the capacitor but the lower potential of the resistor, hence the two signs must be opposite of each other.

Michael D. Edmiston, Ph.D.
Professor of Physics and Chemistry
Bluffton University
Bluffton, OH 45817
(419)-358-3270
edmiston@bluffton.edu
----- Original Message ----- From: "John Denker" <jsd@av8n.com>
To: "PHYS-L Maillist" <phys-l@carnot.physics.buffalo.edu>
Sent: Saturday, February 18, 2006 7:48 PM
Subject: Re: [Phys-l] RC Disharge Analysis


Continuation of previous note:

I just thought of method 3: different circuit, same symbols:

I
____>>>________ V
| |
| -------
| -------
| |
| Z
| Z
| Z
| Z
|___________|___
|
///

V = Q/C capacitor law
V = I R resistor law (Ohm's law)
Q/C + I R = 0 Kirchhoff's loop law, with due regard to signs
dQ/dt = I current is flowing _into_ of the capacitor
dQ/dt = -Q / R C plugging in
Q = Q0 exp(-t / R C) integrating


This just re-reinforces the importance of the diagram in clarifying
the relationship between V, I and dQ/dt.

You can look at the equations and variables until cows come home,
and not understand them unless you have a diagram (or perhaps a
whoooole lot of words explaining what the variables mean).

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